The present invention generally relates to a digital adder. In particular, the present invention relates to an adder of plural bits operated at a high speed and suitable for a microprocessor, a digital signal processor and the like.
Many systems have been conventionally devised with respect to a high speed adding circuit. This is because, as the number of bits of two numbers to be added is increased, it takes time to add these two numbers since a carry signal is propagated from a least significant bit (LSB) to a most significant bit (MSB) in an adder of a carry ripple type constructed by a simple full adder. There are two methods for solving such a problem. One of these methods is a method for increasing an operating speed of the full adder itself. The other method is a method for generating a carry signal of each bit provided to the full adder by another circuit at a high speed. However, since the circuit construction of the full adder is relatively simple, there is a limit in high speed with respect to only an improvement relative to the circuit. A circuit for generating the carry signal of each bit from an input signal is irregularly constructed in many cases, and has a defect of making the circuit construction complicated as the number of bits is increased. In this method, added results of each bit are also obtained by adding the carry signal of each of the bits to the input signal of each of the bits. Accordingly, there is a delay until a sum output is obtained even when the carry signal is generated by a high speed carry signal generating circuit although this delay is slight.
FIG. 6 shows a logic circuit of a 4-bit carry look ahead (CLA) adder as one example of the conventional high speed adder.
This adder is constructed by plural Exclusive-OR gates 3 and plural NAND gates 4 and plural inverters 5. This adder uses the above-mentioned second method. Namely, carry signals C.sub.0, C.sub.1, C.sub.2 from zeroth to second bits are respectively generated by using a CLA circuit from input signals A.sub.0, A.sub.1, A.sub.2, B.sub.0, B.sub.1, B.sub.2 and a carry input signal C.sub.i so that an increase in adding time caused by propagation of the carry signals is prevented. These carry signals are finally added to respective sums of bits A.sub.1, A.sub.2, A.sub.3 and bits B.sub.1, B.sub.2, B.sub.3 of the input signals so that sum outputs S.sub.1, S.sub.2, S.sub.3 are obtained. In this adder, a portion of the circuit is communized by the CLA circuit and the adding circuit of each bit. The carry input signal C.sub.i is used to generate a sum S.sub.0 of the least significant bit.
The carry signals C.sub.0, C.sub.1, C.sub.2 of the respective bits in the 4-bit CLA adder are represented by the following formula. EQU C.sub.0 =G.sub.0 +P.sub.0 C.sub.i EQU C.sub.1 =G.sub.1 +P.sub.1 G.sub.0 +P.sub.1 P.sub.0 C.sub.i EQU C.sub.2 =G.sub.2 +P.sub.2 G.sub.1 +P.sub.2 P.sub.1 G.sub.0 +P.sub.2 P.sub.1 P.sub.0 C.sub.i ( 1)
Here, EQU P.sub.k =A.sub.k B.sub.k (k=0,1,2, . . . ) EQU G.sub.k =A.sub.k .sym.+B.sub.k (k=0,1,2, . . . ) (2)
However, there are the following problems in the above-mentioned conventional adder.
Firstly, there is no regularity in the circuit. A structured design method is generally used in the design of a large scale integrated circuit (LSI). This method is a designing method utilizing regularity of the circuit and the layout of a large circuit is easily made by repeatedly arranging the same circuit block in this method. If a certain large circuit can be realized by a repetitious arrangement of the same relatively small circuit block, it is possible to efficiently reduce a time required to carry out a circuit pattern layout work on a semiconductor wafer, and reliability of the design is improved. However, there is no regularity in the circuit construction of the conventional adder so that it is difficult to apply such a method to the conventional adder.
Secondly, a constant delay time is required from generation of the carry signals of the respective bits until added results are outputted. The carry signals generated by the CLA circuit are finally added to respective sums of the respective bits of input signals so that a sum output is obtained. The Exclusive-OR gate 3 is used in this final addition in the example of FIG. 6. Therefore, a propagating delay time of the Exclusive-OR gate is further required after the generation of the carry signals of the respective bits until the sum output is obtained.